UClinux/Expanding your DE0-NIOS2 system

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Here is an example of controlling the LEDs on the DE0 from uClinux, a simple project that requires no extra hardware or advanced programming to complete, but shows the workflow required in adding custom components.

Contents 1 Adding the PIO port to your SOPC system 2 Connecting the PIO signals in the top level design 3 Connecting the signals to the correct pins 4 Build the project

Adding the PIO port to your SOPC system

Open the project in Quartus, and then run the SOPC Builder tool.

• On the right hand pane find the PIO (Parallel I/O) component and click 'add'.
• In the dialogue box set it to 'output only' and 8 bits wide.
• Join the 's1' port on the PIO with the Avalon bus (under connections).
• Set the base address to "0x04002000".

It should then look like this:

Connecting the PIO signals in the top level design

Alter the top level DE0_nano.v file to include the changes marked with " // <<<<<<<< THIS IS NEW":

module DE0_Nano(
 //////////// CLOCK //////////
 CLOCK_50,

 //////////// SDRAM //////////   // <<<<<<<< THIS IS NEW
 LED,                            // <<<<<<<< THIS IS NEW

 //////////// SDRAM //////////
 DRAM_ADDR,
 DRAM_BA,
 DRAM_CAS_N,
 DRAM_CKE,
 DRAM_CLK,
 DRAM_CS_N,
 DRAM_DQ,
 DRAM_DQM,
 DRAM_RAS_N,
 DRAM_WE_N
);

 //=======================================================
 //  PARAMETER declarations
 //=======================================================


 //=======================================================
 //  PORT declarations
 //=======================================================

 //////////// CLOCK //////////
 input        CLOCK_50;

 //////////// LED ///////////             // <<<<<<<< THIS IS NEW
 output [7:0] LED;                        // <<<<<<<< THIS IS NEW

 //////////// SDRAM //////////
 output [12:0] DRAM_ADDR;
 output [1:0]  DRAM_BA;
 output        DRAM_CAS_N;
 output        DRAM_CKE;
 output        DRAM_CLK;
 output        DRAM_CS_N;
 inout [15:0]  DRAM_DQ;
 output [1:0]  DRAM_DQM;
 output        DRAM_RAS_N;
 output        DRAM_WE_N;

 //=======================================================
 //  REG/WIRE declarations
 //=======================================================
 wire reset_n;

 //=======================================================
 //  Structural coding
 //=======================================================
 assign reset_n = 1'b1;

 DE0_Nano_SOPC DE0_Nano_SOPC_inst(// 1) global signals:
                                  .altpll_io(),
                                  .altpll_sdram(DRAM_CLK),
                                  .altpll_sys(),
                                  .clk_50(CLOCK_50),
                                  .reset_n(reset_n),

                                  // the_altpll_0
                                  .locked_from_the_altpll_0(),
                                  .phasedone_from_the_altpll_0(),

                                  // The PIO_0                         // <<<<<<<< THIS IS NEW
                                  .out_port_from_the_pio_0(LED),       // <<<<<<<< THIS IS NEW

                                  // the_sdram
                                  .zs_addr_from_the_sdram(DRAM_ADDR),
                                  .zs_ba_from_the_sdram(DRAM_BA),
                                  .zs_cas_n_from_the_sdram(DRAM_CAS_N),
                                  .zs_cke_from_the_sdram(DRAM_CKE),
                                  .zs_cs_n_from_the_sdram(DRAM_CS_N),
                                  .zs_dq_to_and_from_the_sdram(DRAM_DQ),
                                  .zs_dqm_from_the_sdram(DRAM_DQM),
                                  .zs_ras_n_from_the_sdram(DRAM_RAS_N),
                                  .zs_we_n_from_the_sdram(DRAM_WE_N));
endmodule

Connecting the signals to the correct pins

Still in Quartus, open the PinPlanner tool and scroll down to the LED[7] - LED[0] section at the bottom.

Enter the pin mappings based on the board's reference manual (or the values below), remembering to set them to 3.3V TTL and 8ma drive:

Close the PinPlanner tool.

Build the project

In Quartus, rebuild the project. You should end up with a new DE0_nano.sof (or DE0_nano_time_limited.sof) to use to configure your board.

Your new system is ready to be downloaded - but now you need software to access the port. See uClinux/Hacking a app for how this is done.